Control register for lane 0
| SHIFT | Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. |
| MASK_LSB | The least-significant bit allowed to pass by the mask (inclusive) |
| MASK_MSB | The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out |
| SIGNED | If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. |
| CROSS_INPUT | If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) |
| CROSS_RESULT | If 1, feed the opposite lane’s result into this lane’s accumulator on POP. |
| ADD_RAW | If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. |
| FORCE_MSB | ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. |
| CLAMP | Only present on INTERP1 on each core. If CLAMP mode is enabled:
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| OVERF0 | Indicates if any masked-off MSBs in ACCUM0 are set. |
| OVERF1 | Indicates if any masked-off MSBs in ACCUM1 are set. |
| OVERF | Set if either OVERF0 or OVERF1 is set. |